INTRODUCTION TO INSTRUCTION SETS
I recently brought the ARM edition of the book Computer Organization and Design by Patterson and Hennessy from library. Half way through the book, I thought of sharing the content of this book in a more elaborated manner by making a series of tutorials on Arm Instruction Set.
So, here’s part one of the series.
- Basic definitions
- Types of Instruction sets Architecture(ISA)
- General purpose register architecture
- Stack architecture
- Accumulator architecture
Ic – Instruction count
Stored Program Concept:
Big-endian: IBM,SPARC, Motorola
Supporting both:MIPS, PowerPC
- PowerPC ( Performance Optimization With Enhanced RISC – Performance Computing) is a RISC instruction set architecture created by Apple–IBM–Motorola alliance, known as AIM.
- Scalable Processor Architecture (SPARC) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems
What’s the difference between ‘Registers’ and Memory?
Here, by registers I mean the registers internal to a CPU. while by, memory i mean RAM.
ARM has 16 internal registers ranging from r0,r1………r12,SP,LR,PC.
Obviously, access to registers is faster then memory thus by using registers for common operations reduces code spill and memory traffic.
MIPS64 has 32 such General purpose registers.
TYPE OF INSTRUCTION SETS:
General purpose register architecture
Let’s take an example of a higher-level statement A=B+C. This statement can be visualized in this architecture as :
i.e here values of B and C (assuming these variables are in memory) are loaded into registers and then operations are performed on registers itself.
This is one of the most widely used architecture with an added advantage that the variable has to loaded from memory only once thus reducing LOAD/STORE instructions.
It is further of 3 types:
- Register-Register type(2 address):
- Here, both operands are registers and output/result of the operation will overwrite one of the register.
- For ex: ADD R1,R2,R1;
- Register-Register type(3 address):
- Here, both operands are registers and result is stored in another register.
- For ex: ADD R1,R2,R3;
- Register-Memory Type:
- Here, one operand is a register and other is the content of a memory location.
There is another type of architecture Memory-Memory Type in which both the operands come from memory, but it’s obsolete nowadays. Both X86 and ARM are general-purpose register type machines , but X86 has Memory-Register Architecture along with some instructions from 2 address Register-register type while ARM(and most of RISC machines) has Register-Register Architecture(both 2 and 3 addresses).
Image courtesy: http://images.slideplayer.com/28/9379293/slides/slide_3.jpg
Here, The instruction A=B+C will be decoded as:
i.e, here instead of registers stack is used. Variables are loaded in and from stack and operations are performed there itself.
It’s very rare to find stack architecture in modern chips rather it’s quite popular in designing interpreters like Java ByteCode
It’s the second most popular architecture after general purpose register(GPR) architecture.
Here, A=B+C will be converted to:
LOAD B into Accumulator
ADD C to Accumulator
Store Accumulator to A
Here, Accumulator can be any register stored directly within ALU. Thus, Accessing it is very fast. It has a drawback that variable need to be loaded from memory again and again in case of multiple operation with same variable.
One of the operand in this architecture is mostly accumulator.
Image courtesy: https://uditagarwal.in/wp-content/uploads/2017/08/isa-architecture-4-638-300×225.jpg
Next post topics:
- RISC,CISC and EPIC / Harvard and Von Neumann architecture
- Instruction set extensions
- Difference between ARM,AVR,MSP430,8085,PIC on basis of Instruction set architecture and organization
Please comment below to suggest any interesting topic for my next post.
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